1. Field of the Invention
The present invention relates to a protection device and a protection method for semiconductor device and, in particular, to a protection device and a protection method for semiconductor device which has excellent resistance to an electrostatic breakdown due to electrostatic discharge (ESD).
2. Description of the Related Art
FIG. 1 is a schematic sectional view showing a conventional MOSFET (metal oxide semiconductor field effect transistor). As shown in FIG. 1, a gate insulation film 101 and a gate electrode 102 are formed on a p type semiconductor layer 100 and on the side thereof, a sidewall 103 is formed. Then, an n type diffusion layer 104 to be a source and an n type diffusion layer 105 to be a drain are formed on the surface of a semiconductor layer 100 at positions where the gate electrode 102 are sandwiched. Also, an NPN parasitic bipolar transistor 106 is comprised of the n type layer 104, the p type semiconductor layer 100, and the n type layer 105. When a positive electrostatic discharge (ESD) is applied to the drain (n type layer 105) of the transistor, a current flows from the drain to the p type semiconductor layer 100 in the direction shown by the arrow a of FIG. 1 and a breakdown occurs. Then, a current flows, as shown by the arrow b of FIG. 1, toward the source (n type layer 104) from the drain and a bipolar action occurs. Then, during the bipolar action, the current concentrates in the vicinity of the surface flows. Since a course in the vicinity of the surface where the current flows is a portion where electric fields that generate around the drain are high, heat generation is concentrated to this portion and the temperature rises and there has been a problem such that an element is broken down when the temperature reaches the melting point of a material used for silicone or wiring.
Priory, an electrostatic protection circuit for protecting a circuit device from the electrostatic breakdown due to the ESD as mentioned above has been provided for a semiconductor integrated circuit. For example, Japanese Patent Laid-Open Publication No.Hei.11-74459 discloses an electrostatic protection circuit which has high surge absorbency without affecting current characteristics of a circuit to be protected.
In the electrostatic protection circuit as set forth in this publication, the protection circuit is connected to an output circuit which is composed of the p-channel MOS and n-channel MOS and has the CMOS of the LDD (lightly doped drain) structure. The protection circuit is composed of a diode with an n type diffusion layer of a high concentration formed on the p well surface, and the cathode thereof is connected to the output terminal while the anode is connected to the earth. Thus, the change in concentration is made steep at the pn junction, whereby the diode having a low breakdown voltage is formed. Also, in the output circuit which is the circuit to be protected, the n type impurities diffusion region to be the source and the n type high concentration impurities diffusion region and n type low concentration impurities diffusion region to be the drains are formed on the p well surface, and the n-channel MOS is formed of these diffusion layers and the gate formed on the p well surface. The source of this n-channel MOS is grounded and the drains are connected to the output terminal. Then, the parasitic diode, in which the cathode is connected to the output terminal and the anode is grounded, is comprised of the above described n type high concentration impurities diffusion region, the n type low concentration impurities diffusion region (drains), and the p well. Furthermore, the parasitic NPN bipolar transistor is formed of the above described n type high concentration impurities diffusion region, the n type low concentration impurities diffusion region (drains), the n type impurities diffusion region (source), and the p well. Thus, in the output circuit, a carrier concentration of the drain region is made low, whereby the diode having a high breakdown voltage is formed.
Accordingly, the semiconductor device having the prior-art electrostatic protection circuit thus constructed comprises the additional diode which starts breakdown at a voltage lower than the breakdown voltage of the parasitic diode in the output circuit, and therefore, the surge current can be absorbed before the parasitic diode in the output circuit breaks down.
The object of the present invention is to provide a protection device for semiconductor device in which resistance to an electrostatic breakdown is enhanced and a protection method for semiconductor device.
A protection device for semiconductor device according to the present invention comprises: a semiconductor substrate; a first conductive type well formed on the surface of said semiconductor substrate; a shallow trench isolation region formed on the surface of said first conductive type well; first and second diffusion layers of second conductive type formed on both sides of the shallow trench isolation region so as to sandwich the shallow trench isolation region, said second diffusion layer comprising a bent portion where electric fields concentrate and a breakdown current flows when a voltage which is higher than a predetermine voltage is applied to the second diffusion layer; and a first conductive type well contact formed on the surface of said first conductive type well and connected to said first diffusion layer.
In the protection device for semiconductor device according to the present invention, when a high voltage is applied to the second diffusion layer, the electric fields concentrate at the bent portion and the breakdown current flows between the bent portion and well contact, and then a voltage at a junction in the first diffusion layer rises, and a current flows between the first and second diffusion layers, however, since the bent portion is formed in the drain region, a breakdown current can flow at a low voltage, and therefore, heat generation due to a rise in voltage in the vicinity of the second diffusion layer can be suppressed and an element can be prevented from breaking down.
On the lower side of the second diffusion layer, a second conductive type electric field retrieving region with an impurity concentration lower than that of the second diffusion layer may be provided.
Also, the bottom portion of the first diffusion layer may be formed to a position deeper than the bottom portion of the second diffusion layer, or it may be formed to a position deeper than the bottom portion of the shallow trench isolation region.
Furthermore, a poly-silicon film may be provided to cover the upper portion of the bent portion.
A protection method for semiconductor device according to the present invention using a protection device for semiconductor device. Said protection device comprising a semiconductor substrate; a first conductive type well formed on the surface of said semiconductor substrate; a shallow trench isolation region formed on the surface of said first conductive type well; first and second diffusion layers of second conductive type formed on both sides of the shallow trench isolation region so as to sandwich the shallow trench isolation region, said second diffusion layer comprising a bent portion; and a first conductive type well contact formed on the surface of said first conductive type well and connected to said first diffusion layer. Said protection method comprises the step of: flowing a breakdown current between said bent portion and said well contact when a voltage which is higher than a predetermine voltage is applied to said second diffusion layer.